Search - vhdl multiplier

[VHDL-FPGA-Verilog] multiply

Description: 好用的浮点乘法器，可完成32位IEEE格式的浮点乘法，经过仿真通过-Easy to use floating-point multiplier, to be completed by 32-bit IEEE format floating-point multiplication, through simulation through
Platform: | Size: 1024 | Author: gulu | Hits:

[VHDL-FPGA-Verilog] risc_cpu

Description: 8位risc cpu的编写，使用quartus软件对其进行写入，里面内置乘法器、除法器等模块-8-bit risc cpu the preparation, use the Quartus software to write, which built-in multiplier, divider modules
Platform: | Size: 814080 | Author: 瑞翔 | Hits:

[Software Engineering] VHDLshili

Description: 本压缩包里含有一4位乘法器及PDF书记一本，其中PDF书记钟含有百例各种VHDL实例-The compression bag containing 4 1 PDF multiplier and a secretary, secretary of the bell which the PDF containing a variety of 100 cases of VHDL examples
Platform: | Size: 2983936 | Author: Eric | Hits:

[VHDL-FPGA-Verilog] multi8x8

Description: 实现了VHDL乘法器，8位乘法操作的完成-VHDL realize a multiplier, an 8-bit multiplication operation completed
Platform: | Size: 3072 | Author: zxzx | Hits:

[VHDL-FPGA-Verilog] xor_mul

Description: 使用列表法，VHDL语言实现的基于多项式基的有限域乘法器，用于AES算法等对有限域乘法有要求的算法-The use of a list of law, VHDL language based polynomial-based finite field multiplier, for the AES algorithm, such as finite field multiplication algorithm has requested
Platform: | Size: 193536 | Author: zxzx | Hits:

[Data structs] jfqs_multiplier

Description: 使用加法器树乘法器实现8位乘法运算，VHDL语言予以实现-Using adder tree multiplier 8 multiplication realize, VHDL language to realize
Platform: | Size: 359424 | Author: zxzx | Hits:

[VHDL-FPGA-Verilog] multiply

Description: 乘法器的vhdl语言描述.本人调试已经通过-Multiplier described in VHDL language. I have been through the debugging
Platform: | Size: 29696 | Author: hjj | Hits:

[Algorithm] xapp371

Description: xilinx里的乘法器ip核程序，booth乘法 wallace tree算法 4-2压缩编码超前进位加法-Xilinx multiplier ip
Platform: | Size: 87040 | Author: 王凯 | Hits:

[Embeded-SCM Develop] Signed32MultiplierV101

Description: 32位元2進位SIGNED乘法器32位元SIGNED乘法器-32-bit 2 binary SIGNED Multiplier Multiplier 32-bit SIGNED
Platform: | Size: 2048 | Author: chen | Hits:

[Algorithm] multiply

Description: 这是我用verilog hdl语言写的浮点乘法器,用的是基4的booth算法,对于部分积使用了5-2压缩和3-2压缩,欢迎大家指点,也欢迎大家把它改成流水线以提高速度.-This is my verilog hdl language used to write floating-point multiplier, using a Radix-4 algorithm for the booth for part of the plot using the 5-2 and 3-2 compression compression, welcomed everyone pointing, also welcomed the U.S. put it into a pipeline to improve speed.
Platform: | Size: 4096 | Author: lanty | Hits:

[VHDL-FPGA-Verilog] 32-bit_multiplier_model

Description: 此程序为32-bit乘法器，另附有VHDL测试程序-This procedure for 32-bit multiplier, followed VHDL test procedures
Platform: | Size: 2048 | Author: zhaohongliang | Hits:

[Other] EDA

Description: 地址译码，状态机的编写，三态输出，布司乘法器-Address decoder, the preparation of state machines, three-state output, cloth Division Multiplier
Platform: | Size: 6144 | Author: 何柳 | Hits:

[VHDL-FPGA-Verilog] mult_piped_8x8

Description: 8位乘8位的流水线乘法器，采用Verilog hdl编写-8 x 8-bit pipelined multiplier, used to prepare Verilog hdl
Platform: | Size: 1024 | Author: 江浩 | Hits:

[VHDL-FPGA-Verilog] Pentium

Description: 这两个分别是8位乘法器的VHDL语言的实现，并经过个人用QUARTUS的验证，另外一个是奔腾处理器的设计思想-The two were 8 multiplier realization of VHDL language and personal use Quartus After verification, another is a Pentium processor design idea
Platform: | Size: 378880 | Author: citydremer | Hits:

[VHDL-FPGA-Verilog] chengfaqi4

Description: 用VHDL实现四位乘法器，不直接用乘法实现，一来节省资源，二来可提高速度！-Use VHDL to achieve four multiplier, not the realization of the direct use of multiplication, one to save resources, and secondly to improve the speed!
Platform: | Size: 1024 | Author: 金 | Hits:

[Crack Hack] mulf2m

Description: 椭圆曲线加密算法中的乘法器的生成，主要功能是实现在素域上的多项式模P(大素数）乘的运算。-Elliptic curve encryption algorithm to generate the multiplier, the main function is to achieve in the Su-domain polynomial module P (large prime numbers) by the operator.
Platform: | Size: 1024 | Author: 傅建新 | Hits:

[VHDL-FPGA-Verilog] GFmultiply

Description: Verilog hdl语言伽罗华域GF（q）乘法器设计，可使用modelsim进行仿真-Language Verilog hdl Galois field GF (q) multiplier design, can use the ModelSim simulation
Platform: | Size: 2048 | Author: 许立宾 | Hits:

[MiddleWare] fq_div

Description: pll 的64倍频锁相环技术用实现倍频从而达到对频率的分频-pll 64 multiplier PLL multiplier used to achieve so as to achieve the sub-band of frequencies
Platform: | Size: 2048 | Author: leo | Hits:

[Other] mux8

Description: 定点八位乘法器的原理图设计，已通过功能仿真！-8 fixed-point multiplier schematic design, functional simulation has passed!
Platform: | Size: 412672 | Author: lxp | Hits:

[VHDL-FPGA-Verilog] serial_multiplex

Description: 绝对好东西，一个VHDL写的任意宽度通用串行乘法器，以最少的资源实现乘法器功能。-Definitely a good thing, a VHDL to write arbitrary width universal serial multiplier, the least amount of resources to achieve multiplier function.
Platform: | Size: 2048 | Author: lin | Hits:

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[VHDL-FPGA-Verilog] multiply

[VHDL-FPGA-Verilog] risc_cpu

[Software Engineering] VHDLshili

[VHDL-FPGA-Verilog] multi8x8

[VHDL-FPGA-Verilog] xor_mul

[Data structs] jfqs_multiplier

[VHDL-FPGA-Verilog] multiply

[Algorithm] xapp371

[Embeded-SCM Develop] Signed32MultiplierV101

[Algorithm] multiply

[VHDL-FPGA-Verilog] 32-bit_multiplier_model

[Other] EDA

[VHDL-FPGA-Verilog] mult_piped_8x8

[VHDL-FPGA-Verilog] Pentium

[VHDL-FPGA-Verilog] chengfaqi4

[Crack Hack] mulf2m

[VHDL-FPGA-Verilog] GFmultiply

[MiddleWare] fq_div

[Other] mux8

[VHDL-FPGA-Verilog] serial_multiplex

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